MAX® II devices contain a two-dimensional row- and column-based architecture toimplement custom logic. Row and column interconnects provide signal interconnectsbetween the logic array blocks (LABs).The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is asmall unit of logic providing efficient implementation of user logic functions. LABsare grouped into rows and columns across the device. The MultiTrack interconnectprovides fast granular timing delays between LABs. The fast routing between LEsprovides minimum timing delay for added levels of logic versus globally routedinterconnect structures.The MAX II device I/O pins are fed by I/O elements (IOE) located at the ends of LABrows and columns around the periphery of the device. Each IOE contains abidirectional I/O buffer with several advanced features. I/O pins support Schmitttrigger inputs and various single-ended standards, such as 66-MHz, 32-bit PCI, andLVTTL.MAX II devices provide a global clock network. The global clock network consists offour global clock lines that drive throughout the entire device, providing clocks for allresources within the device. The global clock lines can also be used for control signalssuch as clear, preset, or output enable.